1. Field of the Invention:
The present invention relates to complementary metal-oxide-semiconductor (CMOS) circuits. More specifically, the present invention relates to translators for CMOS circuits.
While the present invention is described herein with reference to illustrative embodiments for particular applications, it should be understood that the invention is not limited thereto. Those having ordinary skill in the art and access to the teachings provided herein will recognize additional modifications, applications, and embodiments within the scope thereof and additional fields in which the present invention would be of significant utility.
2. Description of the Related Art:
Complementary metal-oxide-semiconductor (CMOS) technology is used in many current digital applications because of the high switching speeds, low power consumption and small die size requirements associated therewith. Unfortunately, it is often necessary to interface CMOS circuits with circuits fabricated in other technologies. These other technologies include TTL (transistor-transistor logic) and ECL (emitter coupled logic). This may be somewhat problematic for many reasons, not the least of which is the fact that each logic family may operate at unique voltage levels. Such is the case with respect to the ECL family. ECL circuits typically operate with a 600 to 800 millivolt potential differential between logic levels. CMOS circuits generally operate at voltage levels between 0 to 5 volts (0 and 5000 millivolts). Thus, when an ECL signal is input to a CMOS circuit, an interface must be used to amplify the input voltage up to CMOS voltage levels. ECL to CMOS translators serve this purpose.
An ECL to CMOS translator amplifies digital ECL signals to CMOS levels. Unfortunately, prior art ECL/CMOS translators are too slow, consume too much power and are too large for many applications. Thus, there is an ongoing need in the art for faster, smaller ECL/CMOS translators which consume less power than conventional designs.